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DANIYAL ARESHIA
Aspiration Statement
I want to flourish in IC industry to be specific Verification Industry up until now.
Core Skills
- Python
- RISCV - Assembly
- SQL
- System Verilog
Academic Awards / Achievements
- Dean's List - 2022
Experience
Leadership / Meta-curricular
- Learning tabla at Centre for South Asian Music
- Director, Logistics, HUMUN 2024
- Director, Logistics, Emerge 2023
Internship / Volunteer Work
- Undergraduate Researcher, “Wally RISC-V Core Verification” Harvey Mudd College (US), 10xEngineers, Habib University (July – Dec 2024)
- Undergraduate Researcher, Office of Research, Habib University (July – Aug 2024)
- Teaching Assistant Engineering Mathematics, (Aug– Dec 2023)
- Undergraduate Researcher, Office of Research, Habib University (June – Aug 2023)
- Teaching Assistant Object-Oriented Programming, CS, Habib University
Publications / Creative Projects
Final Year Project
Project Title
Design Verification through System Verilog
Description
In Capstone I, I worked on an open-source collaborative R&D project, developing the verification tests for 64 I (Integer) and Zbb (Bit Manipulation) extensions of "Wally" RISC-V core developed by Dr Richard Haris at Harvey Mudd College. In Capstone II of our Final Year Project, my team and I are working on developing open-source system Verilog UVM testbench to verify 32-bit RISC V Core running few R, I, S & SB type instructions. Since most of the UVM frameworks are built on paid software therefore developing an open source UVM on Vivado from scratch involves detailed study, broader understanding and hands on work.